The invention relates to a memory device, in particular, an internal data RAM (iRAM) for a microcontroller or microprocessor, to a microcontroller or microprocessor system, and to a method for operating a memory device.
Conventional microcontroller or microprocessor systems include one or several CPUs (central processing units). The CPU(s) are connected to one or several memory devices, e.g., a program memory, and a data memory, etc.
The memory devices may be provided on the same chip, as the CPU(s) (“embedded” microcontroller or microprocessor system, with respective “internal” memories), or alternatively separately from the CPU(s).
The program memory e.g., may store the sequence of instructions to be executed by the CPU(s)—i.e., the program—, and the data memory e.g., respective variables, e.g., variables to be changed by the CPU(s) when executing the program.
In the case of conventional memory devices, in particular conventional semiconductor memory devices, one differentiates between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory)—in particular PROMs, EPROMs, EEPROMs, flash memories, etc.—, and RAM devices (RAM=Random Access Memory or read-write memory), e.g., DRAMs and SRAMs.
In conventional microcontroller or microprocessor systems, as data memory, e.g., a RAM device is used, for instance, an internal dual-port SRAM device with e.g., up to 256 byte or more storage capacity. Alternatively, instead, e.g., an array of flip-flops may be used as data memory.
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address again later.
Since as many memory cells as possible are to be accommodated in a RAM device, one has been trying to realize them as simple as possible.
In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g., of few, for instance 4 transistors for the storing of data (in addition to 2 access transistors), and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element (e.g., a trench capacitor) with the capacitance of which one bit can be stored as charge.
This charge, however, remains for a short time only. Therefore, a “refresh” must be performed regularly, e.g., approximately every 64 ms.
In contrast to that, no “refresh” has to be performed in the case of SRAMs, i.e. the data stored in the memory cell remains stored as long as an appropriate supply voltage is fed to the SRAM.
As the above, in conventional microcontroller or microprocessor systems, as a data memory, e.g., a dual-port SRAM device might be used. A dual-port SRAM (DPSRAM) is a type of SRAM that allows multiple reads or writes to occur at the same time, or nearly the same time, unlike a single-port SRAM which only allows one access at a time. The memory cells of a dual-port SRAM e.g., include 8 transistors, i.e., require more space than single-port SRAM memory cells.
Hence, sometimes it is tried to use SRAMs with single-port memory cells for the implementation of dual-port functionality (“pseudo dual-port SRAMs”, such as e.g., described in U.S. Pat. Nos. 6,259,648 B1, 6,778,462 B1, 6,288,970 B1, US 2004/0190364 A1, JP 9081449A1).
For instance, SRAMs with a partitioned array, and single-port memory cells may be used. Such SRAMs may be provided with two (external) SRAM ports; if the two ports simultaneously attempt to access the same partition (“collision”), then one of the accesses must be delayed.
However, the extra code required due to the partitioning, and the above collision detection lead to relatively high costs.
Further, an SRAM with single-port memory cells might be used, which is accessed at twice the speed of an external clock. Such an SRAM may be provided with two (external) SRAM ports; the first SRAM port might be accessed during the first portion of the clock cycle, and the second SRAM port during the second portion of the clock cycle. However, in this technique, an SRAM with relatively high speed performance is required.
For these or other reasons, there is a need for the present invention.